1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit, and more particularly, to a bandgap circuit that operates at a low voltage, a bias current generation circuit, and a low voltage detection circuit that uses the bandgap circuit.
2. Description of the Related Art
A bandgap circuit is an analog circuit for generating a reference voltage independent of temperature and a power supply voltage. The bandgap circuit is widely used for analog integrated circuits, especially for CMOS analog integrated circuits that constitute a digital and analog mixed integrated circuit.
The bandgap circuit generates a reference voltage that does not depend on temperature by adding a voltage of a forward-biased pn junction and a voltage Proportional To Absolute Temperature (PTAT). Various bandgap circuits are proposed and used in practice.
FIG. 1 is a circuit diagram showing a conventional bandgap circuit. FIG. 2 is a circuit diagram showing another conventional bandgap circuit. FIG. 3 is a circuit diagram showing a conventional bias voltage generator circuit.
In FIG. 1, Q1, Q2, and Q3 denote pnp bipolar transistors. R1 and R2 denote resistors. Vref denotes an output reference voltage. Vdd denotes a positive power supply voltage. GND denotes a ground terminal. NM1 and NM2 denote NMOS transistors. PM1, PM2, and PM3 denote PMOS transistors. “10” denotes a bias voltage applied to the PMOS transistor. “20” denotes a bias voltage applied to the NMOS transistor. “30” through “33” denote internal nodes.
The ratio W/L (W: gate width, L: gate length) of the PM1, PM2, and PM3 is assumed to be equal to each other. The ratio W/L of the NM1 and NM2 is also assumed to be equal to each other, for example. Additionally, the ratio of emitter junction areas of Q1 and Q2 is assumed to be 1:6, for example.
The relation between the forward voltage (Vbe) of the pn junction and absolute temperature (T) can be approximated by the following formula (1):Vbe=Veg−aT  (1)where Veg is the bandgap voltage of silicon, and “a” is temperature dependency of Vbe. Veg is approximately 1.2 V, and “a” is approximately 2 mV/° C.
The relation between an emitter (or diode) current (I) and the forward voltage (Vbe) of a bipolar transistor can be approximated by the following formula (2):I=I0*exp (qVbe/kT)  (2)where I0 is a constant proportional to the area of the emitter, q is the charge of an electron, and k is the Boltzman constant.
In FIG. 1, the gate electrodes of PM1 and PM2 are common, and as a result, the same current flows through PM1, PM2, NM1, NM2, Q1, and Q2. Since the same current flows through NM1 and NM2, a voltage at the internal node 30 and a voltage at the internal node 31 are equal. Because the ratio in the junction area between Q1 and Q2 is 1:6, the current that flows through Q1 and Q2 may be obtained as follows:Q1 current=I0*exp (qVbe1/kT)Q2 current=6*I0*exp (qVbe2/kT)where Vbe1 is the Vbe of Q1 and Vbe2 is the Vbe of Q2. By setting the above Q1 current and Q2 current equal, and resolving the equation for Vbe1−Vbe2, voltage VR1 between both ends of the resistor R1 is obtainable as follows:VR1=(kT/q)*ln(6)  (3)
Accordingly, the current Ip that flows through PM1 and PM2 is:Ip=(1/R1)*(kT/q)*ln(6)  (4)where R1 is the resistance of R1. Because the same current flows through PM3, the voltage drop VR2 at the resistor R2 is:VR2=(R2/R1)*(kT/q)*ln(6)  (5)where R2 is the resistance of R2.
The sum of the voltage drop VR2 by the resistor R2 and the Vbe of Q3 is a reference voltage Vref. As temperature rises, the forward voltage Vbe of pn junction is reduced (negative temperature dependency) as shown in formula (1), but the voltage drop VR2 at the resistor R2 increases as shown in formula (5). If the values of elements are appropriately determined, the reference voltage Vref becomes independent of temperature. In such a case, the reference voltage Vref becomes approximately 1.2 V, which voltage is the bandgap voltage of silicon.
As described above, the conventional bandgap circuit shown in FIG. 1 can generate a bandgap voltage that does not depend on temperature by appropriately determining the junction area ratio of PM1, PM2, PM3, NM1, NM2, Q1, and Q2, and the values of R2 and R1.
The conventional circuit shown in FIG. 2, although different in structure from that shown in FIG. 1, can generate a reference voltage that does not depend on temperature in the same manner. The circuit shown in FIG. 2 is disclosed in the following documents: Japanese Laid-Open Patent Applications No. 8-186484 and No. 2001-147725. Similar circuits are disclosed in the following documents:
Japanese Laid-Open Patent Applications:
No. 2002-99336, No. 2003-78366, No. 10-198447, No. 5-204479, and No. 6-309052.
1) G. Tzanateas, C. A. T. Salama, and Y. P. Tsividis, “A CMOS Bandgap Voltage Reference,” IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 3, pp. 655–657, June 1979, for example.
In FIG. 2, D1 denotes a diode. R1, R2, and R3 denote resistors. Vref and Vdd denote an output reference voltage and a positive power supply voltage, respectively. GND denotes a ground terminal. NM3 and NM4 denote NMOS transistors. PM1, PM2, PM3, PM7, and PM8 denote PMOS transistors. “10” denotes a bias voltage of the PMOS transistors PM1 and PM2. “21” denotes the bias voltage of the NMOS transistors NM3 and NM4. “33”, “35”, and “90” denote internal nodes. Components identical to those shown in FIG. 1 are referred to by the same reference symbols in FIG. 2.
For example, the ratio W/L (W: gate width, L: gate length) of PM1, PM2, and PM3 is assumed mutually equal. The W/L ratio of NM3 and NM4 is assumed 1:6, for example. NM3 and NM4 are designed to operate in a sub-threshold region.
Assuming a voltage between the gate and the source of an NMOS transistor is Vgs, the relation between a drain current ID and the voltage Vgs in the drain region can be approximated as follows:ID=I0*exp (qVgs/nkT)  (6)where I0 is a constant proportional to W, “q” is the charge of an electron, “k” is the Boltzmann constant, T refers to absolute temperature, “n” refers to a constant depending on the capacitance of an oxide layer and the capacitance of a depletion layer. The “n” of an NMOS transistor is generally about 1.3, for example.
The gate of PM1 and the gate of PM2 are connected to each other, and as a result, the same current flows through PM1, PM2, NM3, NM4, and R1. Since the current flowing through NM3 is equal to the current flowing through NM4, and both the ratio W/L of NM3 and the ratio N/W of NM4 are assumed to be 1:6, a voltage VR1 between both ends of the resistor R1 can be approximated in the same manner as the above formula (3) as follows:VR1=(nkT/q)*ln(6)  (7)
Because the voltage VR1 between both ends of the resistor R1 is computable by the formula (7), a current Ip that flows through PM1 and the same current Ip that flows through PM2 can be expressed as follows:Ip=(1/R1)*(nkT/q)*ln(6)  (8)
The same current Ip flows through PM3. The formula (8) shows that, if the temperature dependency of resistance is ignored, the current Ip that flows through PM3 is proportional to temperature. Because the same current flows through the resistor R2 and the diode D1, the reference voltage Vref can be expressed by the following formula:Vref=Vbe+(R2/R1)*(nkT/q)*ln(6)  (9)where Vbe is a forward voltage of D1, and R2 is the resistance of the resistor R2.
Vbe negatively depends on temperature. Accordingly, if parameters are appropriately determined so that the term (R2/R1)*(nkT/q)*ln(6) cancels the negative dependency of Vbe on temperature, the reference voltage Vref can be made indifferent of temperature. According to the above arrangements, the reference voltage Vref is made equal to the bandgap voltage of silicon, which is approximately 1.2 V.
As described above, if parameters of PM1, PM2, PM3, NM3, NM4, R2, and R1 are appropriately determined, the conventional circuit shown in FIG. 2, although it is relatively simple, can generate a bandgap voltage independent of temperature. The accuracy of the circuit shown in FIG. 1 is high because it uses the bipolar transistors. However, the circuit shown in FIG. 1 requires a high voltage to operate the PMOS transistor, the NMOS transistor, and the bipolar transistor connected in series. The circuit shown in FIG. 2 operates at a low voltage, and solves the above problem of the circuit shown in FIG. 1.
FIG. 3 is a circuit diagram showing a conventional bias current generator circuit for generating a bias current. The bias current generator circuit shown in FIG. 3 generates a bias current proportional to absolute temperature. For example, the circuit including PM3, R2, and D1 shown in FIG. 2 generates a reference voltage Vref using the bias current generated by the bias current generator circuit shown in FIG. 3. Components identical to those shown in FIG. 2 are referred to by the same reference symbols in FIG. 3.
The conventional bias current generator circuit shown in FIG. 3 generates a bias current proportional to absolute temperature (as computed by formula (8)) in the same manner as the conventional bandgap circuit shown in FIG. 2.
A portion BLK1 of the circuit shown in FIG. 3 operates as a starting-up circuit. The other portion of the circuit including a loop of PM1, PM2, NM3, NM4, and R1 is stable at a stable point computed by the formula (8), but is also stable at another stable point in which no current flows at all. The starting-up circuit BLK1 solves this problem.
When the circuit is at the undesired stable point in which no current flows, a voltage at an internal node 10 becomes Vdd, and a voltage at an internal node 21 becomes GND. Since NM6 is off in this case, a current that flows through PM4 retains a voltage at an internal node 34 at Vdd. When the voltage at the internal node 34 becomes Vdd, NM5 is turned on, and a current starts flowing through PM2. When the current starts flowing through PM2, a current starts flowing through PM1, and the circuit is transferred to the stable point of the formula (8).
When a current starts flowing through PM1, PM2, NM3, NM4, and R1, a current starts flowing through NM6. A voltage at the internal node 34 becomes about the level of GND, and as a result NM5 is turned off. According to the above arrangements, the starting-up circuit BLK1 is cut off the loop including PM1, PM2, NM3, NM4, and R1.
FIG. 4 is a circuit diagram showing yet another conventional bandgap circuit.
In FIG. 4, Q1 and Q2 denote pnp bipolar transistors. R1, R2, and R2′ denote resistors. Vref and Vdd denote an output reference voltage and a positive power supply, respectively. GND denotes a ground terminal. PM1 and PM2 denote PMOS transistors. “11” denotes the bias voltage (output of an operational amplifier) of the PMOS transistors. “30”, “31”, and “32” denote internal nodes. OP1 denotes an operational amplifier. Components identical to those shown in FIG. 1 are referred to by the same symbols in FIG. 4.
For example, the ratio W/L (W: gate width, L: gate length) of PM1 and PM2 is assumed mutually equal. The junction area ratio of Q1 and Q2 is assumed 1:6, for example. The resistance of the resistor R2 and the resistance of the resistor R2′ are assumed equal to each other.
The base-emitter voltage Vbe of a bipolar transistor and the forward voltage Vbe of pn junction are related as shown in the formula (1). The emitter current I of the bipolar transistor and the voltage Vbe are related as shown in the formula (2).
Since the gate of PM1 and the gate of PM2 are connected, the same current flows through PM1, PM2, Q1, Q2, R1, R2, and R2′. The negative feedback of OP1 makes a voltage at the node 30 and a voltage at the node 31 substantially equal to each other, and makes the circuit stable. Since the voltage at the node 30 and the voltage at the node 31 are equal to each other, and the junction area ratio between Q1 and Q2 is 1:6, a voltage VR1 between both ends of the resistor R1 can be computed as the formula (3). A current Ip as shown by the above formula (3) flows through PM1 and PM2. Because the current Ip flows through the resistor R2, a voltage drop VR2 caused by the resistor R2 is expressed by the above formula (5). A reference voltage Vref is the sum of the voltage drop VR2 caused by the resistor R2 and the Vbe of Q3. The forward voltage Vbe of the pn junction negatively depends on temperature, and the voltage drop VR2 caused by the resistor R2 has a positive dependency on temperature. Accordingly, if parameters are appropriately determined, the reference voltage Vref can be made independent of temperature. The voltage Vref becomes about 1.2 V, which corresponds to the bandgap voltage of silicon. As described above, if parameters such as the sizes of PM1 and PM2, the junction area ratio between Q1 and Q2, and the resistances of R2 and R1 are appropriately determined, the simple conventional circuit shown in FIG. 4 using an operational amplifier can generate the bandgap voltage independent of temperature. The conventional bandgap circuit using an operational amplifier is disclosed in the following documents:
2) K. N. Leung, and P. K. T. Mok, “A Sub-1-V 15-ppm/CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Devices,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 4, pp. 526–530, April 2002.
3) A. Boni, “Op-Amps and Startup Circuits for CMOS Bandgap References With Near 1-V Supply,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 10, pp. 1339–1343, October 2002.
4) H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 670–674, May 1999.
One of the applications of the bandgap circuits shown in FIGS. 1, 2, and 4 is the detecting of a low voltage. A determination can be made whether a power supply voltage, for example, is lower than a predetermined voltage by dividing the power supply voltage and comparing the divided power supply voltage with the reference voltage of a bandgap circuit that is independent of the power supply voltage and temperature. If a determination is made that the power supply voltage is lower than the predetermined voltage, the operation of circuits to which the power supply voltage is provided may be stopped for avoiding any erroneous operation.